The present invention relates to digital communications, and more particularly, to the indication of a start of frame pulse location within a frame of digital data in a synchronous system. The invention is advantageous for configuring a digital communication system to accommodate differing start of frame pulse locations.
Existing propriety digital communications systems are typically designed with a start of frame pulse location at a fixed byte location in the frame. Moreover, the start of frame pulse location may be different between communication systems requiring equipment manufacturers to provide system specific equipment designs.
Accordingly, there exists a definite need for a digital communication system that can accommodate differing start of frame pulse locations within framed synchronous digital data. The present invention satisfies these needs and provides further related advantages.
The present invention is embodied in an apparatus, and related method, for providing a reconfigurable frame counter that can accommodate differing start of frame pulse locations in a synchronous communication system. The frame counter may be integrated with existing devices thus providing a cost effective advance in the functionality of existing communication devices.
The reconfigurable frame counter includes a multiplexer, a byte processor and a frame counter. The multiplexer byte interleave multiplexes a plurality of, lower data rate SONET signals to generate a higher data rate SONET signal of framed data bytes. The byte processor processes transport overhead bytes of the higher data rate SONET signal in accordance with predetermined frame byte count values. The frame byte counter counts clock pulses that are each associated with the arrival of a framed data byte and generates a frame byte count value that corresponds to a frame byte location of the currently received framed data byte. The frame byte counter has a programmable configuration start address value and a synchronization pulse input and, in response to a synchronization pulse on the synchronization pulse input, the frame byte counter counts the clock pulses with an initial start count equal to the configuration start address value such that the frame byte count value indicates the frame byte location of the currently received framed data byte.
Further, the frame byte counter may include a configuration start value latch, a configuration start address input and a write strobe input. The configuration start value latch latches the configuration start address value on the configuration start address input in response to a write strobe pulse on the write strobe input for programming the initial start count.
The lower data rate SONET signals may be four OC-12 signals that are byte interleave multiplexed into an OC-48 signal. The byte processor processes the B1 bytes of the OC-48 signal. The configuration start address value may be associated with a third A2 byte or with a first payload data byte of the OC-48 signal such as byte location number 145 of the OC-48 signal.
Other features and advantages of the present invention should become apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.